EASii IC announces earth-segment satellite communication modem ASIC, EZID211 also known as Oxford-2
EASii IC announces its satellite modem ASIC, EZID211 also known as Oxford-2. The Oxford-2 is aimed at the earth-segment satellite communication market. Targeted applications include: internet via satellite user terminals covering GEO, MEO and LEO constellations, aero-mobile, earth observation, cellular backhaul, IP trunking, IOT and many other applications. The Oxford-2 is compliant with the DVB-S2 standard ETSI EN 302 307-2 and implements the latest S2X, adaptive coding and modulation (ACM), Very Low Signal to Noise Ratio (VLSNR) and super frame functionality.
The receiver section comprises a dual L-band tuners and dual high symbol rate demodulators. The RF inputs support the frequency range 950-2150MHz whilst the demodulators are capable of demodulating signals from below 1Msps through to 500Msps in symbol rate. Data throughput of up to 720M channel bits per second (uncorrected data) for each demodulation chain is supported which provides for an aggregate user throughput in excess of 1Gbit per second for the chip as a whole. Multiple Oxford ICs may be used in tandem if higher rates are required. The VLSNR capabilities allow signal reception from around -10dB whilst the highest coding mode (256APSK) enables up to 20dB carrier to noise ratio, the standard defines over 90 modulation and coding combinations which allow fine-grained optimization of efficiency vs robustness over a very wide range of reception conditions.
The device includes a transmit chain which implements an IQ streamer, an S2X modulator and an RCS2 modulator.
Many of the peripheral functions such as crystal oscillator, antenna control, power supplies have been integrated to ensure the lowest cost of implementation and ownership. For example, the device integrates a Network Clock Recovery (NCR) subsystem which is used to synchronize return channel burst mode signals to the satellite. Furthermore, a choice of LVDS and RGMii interfaces is provided for to cater for both high performance FPGA based and low-cost microprocessor-based applications.
The device is fabricated on 40nm CMOS low-power process and packaged in a 13x13mm VQFPN-mr 168 package. The power consumption is a function throughput and reception conditions and ranges from below 2 Watts up to 5 Watts at full loading.
The first silicon was received in EASii IC labs in mid-September 2022 has now successfully passed all functional checks. The full validation, characterization and industrialization phase has now started. Mass production for selected customers is scheduled for the first half 2023.
The device will be demonstrated at the Electronica exhibition in Munich on the 16th and 17th November in Hall 2 booth 148.